Senior RTL Design Engineer
Senior RTL Design Engineer
MosChip SemiconductorThis job is no longer accepting applications
Job Description
Job Description:
Role: Senior RTL Design Engineer
Experience: 6 - 12 Years of Experience
Location: Bangalore/ Hyderabad
Work Mode: Work from office
Required Skills
- Experience in Logic design / RTL coding is a must.
- Experience is SoC design and integration for complex SoCs is a must.
- Experience in Verilog/System-Verilog is a must.
- Experience in Multi Clock designs, Asynchronous interface is a must.
- Experience in using the tools in ASIC development such as Lint and CDC.
- Experience in Synthesis / Understanding of timing concepts is a plus.
- Experience in ECO fixes and formal verification.
- Should have knowledge of AMBA protocols - AXI, AHB, APB, SoC clocking/reset architecture.
- Excellent oral and written communications skills.
- Proactive, creative, curious, motivated to learn and contribute with good collaboration skills
More Info
Job Type:
Industry:
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Key Skills
Asynchronous interface
ECO fixes
SoC clocking reset architecture
Logic design RTL coding
SoC design and integration
Multi Clock designs
System-Verilog
About Company
Skills:
telemetry , Verilog, System Verilog, Debug, secure MMIO access-control, AXI-Lite, transaction error handling, Axi, APB, EDA Tools, parity ECC schemes, RTL Coding, privilege-based filtering, firewall logic, RAS concepts, Mentor Graphics, Cadence, Synopsys