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Job Description:
Role: Senior RTL Design Engineer
Experience: 6 - 12 Years of Experience
Location: Bangalore/ Hyderabad
Work Mode: Work from office
Required Skills
Job ID: 151459095
Skills:
Verilog, System Verilog, Cadence JasperGold, digital-analog interface, UPF, LEC, clock gating, Linting, PIPE interface standard, high-speed SerDes architectures, formal verification, calibration algorithms, Synopsys SpyGlass, low-power design techniques
Skills:
Verilog, Pcie, Low power estimation, Low power RTL design, Microarchitecture synthesis, LINT, Timing Closure, Rtl Design, CXL, cdc
Skills:
Verilog, RDC, LINT, ISO 26262, Safety analysis methodologies, Functional Safety concepts, RTL design and integration, systemverilog, ASIL requirements, Synthesis checks, cdc, Micro-architecture development
Skills:
Sdlc, Agile Methodologies, C, Java, Soc Architecture, Verilog, Python, Git, RTL integration, HDLs, Verification Tools, digital design principles, ASIC Design, VHDL, DevOps practices
Skills:
Ovm, Perl, Python, physical implementation, Synthesis, cdc, verification methodologies, static design checks, Verilog Hdl, Linting, Timing Analysis, Uvm, systemverilog, power management techniques, Dft, RDC, X-Propagation, design specifications, digital hardware design