Verilog, System Verilog, Cadence JasperGold, digital-analog interface, UPF, LEC, clock gating, Linting, PIPE interface standard, high-speed SerDes architectures, formal verification, calibration algorithms, Synopsys SpyGlass, low-power design techniques

Verilog, Pcie, Low power estimation, Low power RTL design, Microarchitecture synthesis, LINT, Timing Closure, Rtl Design, CXL, cdc

Verilog, RDC, LINT, ISO 26262, Safety analysis methodologies, Functional Safety concepts, RTL design and integration, systemverilog, ASIL requirements, Synthesis checks, cdc, Micro-architecture development

Sdlc, Agile Methodologies, C, Java, Soc Architecture, Verilog, Python, Git, RTL integration, HDLs, Verification Tools, digital design principles, ASIC Design, VHDL, DevOps practices

Ovm, Perl, Python, physical implementation, Synthesis, cdc, verification methodologies, static design checks, Verilog Hdl, Linting, Timing Analysis, Uvm, systemverilog, power management techniques, Dft, RDC, X-Propagation, design specifications, digital hardware design

Usb, DDR, Pcie, Verilog, Ethernet, LINT, Sta, Synthesis, cdc, UCIe, systemverilog, spyglass, VHDL, formal checking, RDC, HBM

Spi, Uart, Verilog, Arm, System Verilog, I2c, Gpio, USB standards, Synopsys, ASIC design flow, Interconnect fabrics, Arteris fabrics, RTL Coding, Cadence, Scripting in Perl, Peripheral interface IPs, QSPI, I3C, System Verilog assertions, NoC architecture, Third-party IP integration, Axi