Job Description
We are seeking a strong Digital Physical Design Engineer to drive block-level physical implementation of complex SoCs/ASICs across advanced nodes.
The role involves hands-on ownership from synthesis to tape-out, ensuring closure across timing, power, area, and signoff quality, while guiding junior engineers and contributing to flow improvements.
Responsibilities
- Execute and own physical design activities including floorplanning, power planning, placement, CTS, routing, and STA
- Drive timing closure across multi-mode, multi-corner scenarios
- Perform physical verification (DRC, LVS, Antenna) and resolve violations to achieve clean signoff
- Conduct power integrity analysis (IR drop, EM) and optimize PDN for robust designs
- Support DFT implementation and ensure test structure integration
- Analyze and resolve timing, congestion, power, and signal integrity issues
- Execute ECOs and support tape-out readiness under tight schedules
- Develop and maintain automation scripts to improve flow efficiency
- Contribute to methodology improvements and standardization across projects
- Review implementation strategies, constraints, and floorplans of junior engineers and provide technical guidance
Qualification
- Bachelor's or Master's degree in Electronics / Electrical Engineering or related field
- 49 years of hands-on experience in digital physical design of complex SoCs or ASICs
- Strong proficiency with industry-standard EDA tools (Fusion Compiler / Innovus / ICC2, Tempus / PrimeTime, Voltus / RedHawk, Calibre)
- Solid understanding of:
- Floorplanning and power planning strategies
- Placement and routing optimization
- Clock tree synthesis (CTS)
- Static Timing Analysis (STA) and timing closure techniques
- Physical verification and reliability checks
- Experience with advanced nodes (16nm / 7nm / 5nm preferred)
- Strong scripting skills (Tcl required; Python/Perl preferred)
Soft Skills
- Ability to independently close timing- or congestion-critical blocks
- Structured debugging approach for timing, IR/EM, and tool-related issues
- Clear communication of risks and closure status
- Capability to mentor junior engineers and support technical reviews
- Strong ownership mindset and execution discipline.
- Ability to manage multiple deliverables under tight timelines.
