Python, Tcl, EDA Tools, PrimeClosure, floorplanning, CTS, Innovus, Aspen, Sta, ICC2, IO Timing ECO, Physical Design, Tempus, Postroute Optimization, Seahawk, Placement, Timing Closure, DRC closure, EMIR drop

redhawk , Shell, Tcl, Verilog, PERL, Innovus, floorplan exploration and optimization, Starrcxt, place and route methodologies, physical implementation and analysis tools, Fusion Compiler, power integrity and reliability analysis, Calibre, VHDL, low power physical design flows and methodologies, timing and signal integrity analysis, metal-only ECO implementation, power grid planning and implementation, timing optimization and timing closure, placement and optimization, Clock Tree Synthesis

Synthesis, PNR, Timing Closure, Pv, EM-IR Signoff