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eInfochips (An Arrow Company) Hiring Physical Design Engineer
Experience - 5+ Years
Location- Across Locations
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Job description is as below:
* Block level Physical Design Implementation from RTL to GDSII or Netlist to GDSII,
* Block level Physical Signoff,
* Block level Timing Signoff and ECO generation.
* Block level Power signoff.
* Good skill on Automation (Perl/Tcl/Awk/Python)
* Able to provide technical guidance to Junior Engineer and lead 4-6 engineers.
* Must have led small project team.
* Good in communication skill as he/she would be single point of contact for client.
* NO WORK FROM HOME.
Job ID: 146087105
Skills:
power optimization , Perl, Scripting, Python, Tcl, Cadence, Mentor, Timing Analysis, Physical Design, Signal Integrity, EDA Tools, Synopsys
Skills:
redhawk , Perl, Tcl, Dc, Deep sub-micron designs, Pt, Logic equivalence checking, Formality, VSLP, LVS, ICC, STA timing, Physical Design, Calibre, Timing Closure, Synthesis, SOC design, DRC, Place And Route, Low Power checking
Skills:
Tcl, Python, PERL, Seahawk, Tempus, primetime, Innovus, ICC2
Skills:
Static Timing analysis, Perl, Tcl, Clock Planning, SoC designs, Power Plan, Digital place and route, Floor Planning, Clock Tree Synthesis, Parasitic Extraction, PnR Signoff
Skills:
Floorplan convergence, Electrical, low power designs, scripting with TCL, automations
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