power optimization , Perl, Scripting, Python, Tcl, Cadence, Mentor, Timing Analysis, Physical Design, Signal Integrity, EDA Tools, Synopsys

redhawk , Perl, Tcl, Dc, Deep sub-micron designs, Pt, Logic equivalence checking, Formality, VSLP, LVS, ICC, STA timing, Physical Design, Calibre, Timing Closure, Synthesis, SOC design, DRC, Place And Route, Low Power checking

Tcl, Python, PERL, Seahawk, Tempus, primetime, Innovus, ICC2

Static Timing analysis, Perl, Tcl, Clock Planning, SoC designs, Power Plan, Digital place and route, Floor Planning, Clock Tree Synthesis, Parasitic Extraction, PnR Signoff

Floorplan convergence, Electrical, low power designs, scripting with TCL, automations

Computer Architecture, Verilog, Tcl, Python, Perl, Cadence Innovus, EDA Tools, digital logic, Physical Design, Methodology

Dsp, C++, Soc, Route, Python, Fc, Tcl, power analysis, Physical Design, Floorplan, Innovus, formal verification