Senior Physical Design Engineer

Best Nanotech is expanding its VLSI team in Bengaluru!

We are looking for a Senior Physical Design Engineer with 7+ years of experience to take ownership of complex high-speed blocks from Netlist to GDSII in advanced technology nodes (5nm/3nm).

Position: Senior/Lead Physical Design Engineer

Location: Bengaluru (On-site/Hybrid)

Experience: 7+ Years

Your Impact:

• Ownership: Lead the complete PnR flow (Floorplan, Placement, CTS, Routing) for multi-million gate IP/SoC blocks.
• Closure: Drive timing, power, and physical signoff (DRC/LVS) to convergence.
• Optimization: Solve complex congestion, IR drop, and signal integrity issues in FinFET technologies.
• Mentorship: Guide junior engineers on flow methodologies and debug strategies.

Technical Requirements:

Deep expertise in Cadence Innovus or Synopsys ICC2.

Strong background in STA (PrimeTime/Tempus) and constraint validation.

Hands-on experience with Low Power Design (UPF/CPF) and IR/EM analysis (Redhawk/Voltus). Proven track record of tape-outs in 7nm/5nm or below.

Scripting proficiency (Tcl/Python/Perl) to automate flows.

How to Apply: If you are a problem-solver who enjoys closing clean designs, send your resume to [[Confidential Information]] or apply via the link in the comments.

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