9-10 years experience with Bachelor's degree in Electronics Engineering or equivalent
Good experience in Physical Design with innovus tool
Hands-on experience in developing and modifying PD-flow/EDA-tools scripts/recipes using TCL/SHELL/PYTHON programming languages.
Experience in developing PD metrics dashboard scripts for QOR tracking is a plus
Experience in modifying STA constraints to check timing closure feasibility
Experience in various clock implementation strategies (Multi-point CTS, Flex-H, Custom-CTS) for meeting block level and full chip level latency and skew targets
Experience in FinFET & Dual Patterning nodes such as 16/14/10/7/5/3nm
Strong leadership skills to lead a team of physical design engineers in the development and execution of complex projects
Proven track record of delivering high-quality physical design solutions within tight deadlines
Ability to collaborate effectively with cross-functional teams to ensure successful project outcomes
