static timing analysis, routing, Perl, Python, Tcl, Innovus, Fusion Compiler, floorplanning, ICC2, LVS, DRC, Placement, Parasitic Extraction, Clock Tree Synthesis

Mentor-Calibre, Physical Verification, pegasus, Cadence Innovus, EM IR drop analysis, Static Dynamic IR analysis, EDA tool automation, Voltus

power optimization , Eda, Tcl Scripting, Python, power analysis, Sta, Agentic AI methodologies, DVFS, LEC, AI-driven optimization, Place And Route, UPF, Physical Verification, Timing Power closure, Asic Physical Design, Physical Verification, full chip and block level floor-planning, Eco, multi-Vt power domains, RTL to GDS Flow, CPF, LLM-assisted debugging, autonomous agents

Routing, Python, Tcl, CTS, floorplanning, Placement Optimization, Antenna Density, LVS, Power Planning, IC Validator, Calibre, Physical Verification, Signoff Closure, Physical Design, ERC, Timing Closure, ECO Implementation, DRC