Senior Memory Layout Engineer

Location: Bengaluru, India

Experience: 5–12 Years

Role Overview

We are looking for experienced Senior Memory Layout Engineers with strong hands-on expertise in full-custom memory layout development at advanced technology nodes, particularly FinFET technologies. The role involves implementing and optimizing SRAM, register-file memories, and associated peripheral circuits at lower technology nodes, with a focus on layout quality, area efficiency, parasitic optimization, and physical verification closure.

Key Responsibilities

Develop and optimize full-custom layouts for SRAM bitcells, memory arrays, register files, and memory peripheral circuits.
Work on advanced technology nodes, including FinFET-based processes, with exposure to lower-node design constraints.
Implement layouts for sense amplifiers, decoders, write drivers, and other memory circuits.
Optimize layout for area, parasitics, matching, routing efficiency, and power-performance requirements.
Perform layout integration, floorplanning, placement, and routing for complex memory blocks.
Execute physical verification, including DRC, LVS, ERC, and antenna checks.
Perform parasitic extraction and support post-layout simulation and design closure.
Resolve complex layout violations and advanced-node design-rule challenges.
Collaborate with circuit design, characterization, and process teams to achieve memory design targets.
Support layout sign-off and tape-out activities while ensuring compliance with foundry rules and reliability requirements.

Required Technical Skills

5–12 years of hands-on experience in full-custom IC layout, preferably SRAM or memory layout.
Strong exposure to advanced FinFET technology nodes and lower-node layout implementation.
Expertise in SRAM bitcell layout, memory arrays, register files, and peripheral circuits.
Strong understanding of CMOS layout fundamentals, design-rule constraints, matching, symmetry, and parasitic-aware routing.
Hands-on experience with physical verification flows: DRC, LVS, ERC, and antenna checks.
Experience with parasitic extraction and layout debugging.
Proficiency in Cadence Virtuoso and relevant physical verification and extraction tools.
Understanding of advanced-node layout challenges, including restrictive design rules, routing congestion, and parasitic control.

Preferred Qualifications

Experience with advanced FinFET nodes such as 7nm, 5nm, 4nm, or 3nm, depending on project requirements.
Exposure to high-density SRAM, low-power memory design, and memory compiler layouts.
Experience with foundry-specific sign-off requirements and advanced-node physical verification.
Knowledge of post-layout simulation, layout-dependent effects, and memory characterization flows.
B.E./B.Tech or M.E./M.Tech in Electronics, Electrical Engineering, VLSI, or a related discipline.