About Marvell

Marvell's semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, and carrier architectures, our innovative technology is enabling new possibilities.

At Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead.

Your Team, Your Impact

As an Analog Layout Senior Staff Engineer with Marvell, you'll be a member of the Central Engineering business group. If you picture Marvell as a wheel, Central Engineering is the center hub providing IP to be used by all the other spokes on that wheel, including Automotive, Storage, Security, and Networking. You'll be part of a small analog team making a big impact on this organization. Additionally, Marvell has the perfect size and scale for you to learn several aspects of engineering that will be new to you, but also have the time and freedom to dive deep into the details of your specialization on most projects.

What You Can Expect

Play a leading role in developing full-custom memory layout and sign-off verification flows
Collaborate with circuit designers globally to translate schematics into efficient, high-performance layouts and drive end-to-end ownership from floor planning to tape-out.
Ensure physical verification closure by resolving DRC, LVS, ERC, and antenna violations perform EMIR analysis and implement fixes for IR drop and electromigration.
Lead layout reviews, mentor junior engineers, and promote best practices, optimization techniques, and design rule compliance while fostering knowledge-sharing and process improvements.
Stay ahead of evolving technologies and tools, and develop automation scripts (Perl, Tcl, SKILL) to enhance productivity and consistency.

What We're Looking For

Education: BE/B.Techor MS/M.Techin Electrical/Electronics Engineering, Microelectronics, or related fields 8+ years of hands-on SRAM compiler layout experience
Strong understanding of semiconductor process technologies, device physics, and layout effects in advanced nodes.
Full-custom memory layout development for SRAM compiler blocks
Complete physical verification across EM, IR, LVS, DRC and related flows
Work closely with circuit, architecture, and verification teams
Drive layout quality, constraints, and design-rule adherence
Support optimization, debug, and design-rule closure
Proficiency with Cadence Virtuoso and industry-standard EDA tools scripting skills (Perl, Tcl, SKILL) for automation are a plus.
Excellent communication skills to collaborate with global teams and provide clear status updates.
Self-motivated, adaptable, and eager to learn in a dynamic environment.

Additional Compensation and Benefit Elements

With competitive compensation and great benefits, you will enjoy our workstyle within an environment of shared collaboration, transparency, and inclusivity. We're dedicated to giving our people the tools and resources they need to succeed in doing work that matters, and to grow and develop with us. For additional information on what it's like to work at Marvell, visit our page.

All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, sexual orientation, gender identity, disability or protected veteran status.

Interview Integrity

To support fair and authentic hiring practices, candidates are not permitted to use AI tools (such as transcription apps, real-time answer generators like ChatGPT or Copilot, or automated note-taking bots) during interviews.

These tools must not be used to record, assist with, or enhance responses in any way. Our interviews are designed to evaluate your individual experience, thought process, and communication skills in real time. Use of AI tools without prior instruction from the interviewer will result in disqualification from the hiring process.

This position may require access to technology and/or software subject to U.S. export control laws and regulations, including the Export Administration Regulations (EAR). As such, applicants must be eligible to access export-controlled information as defined under applicable law. Marvell may be required to obtain export licensing approval from the U.S. Department of Commerce and/or the U.S. Department of State. Except for U.S. citizens, lawful permanent residents, or protected individuals as defined by 8 U.S.C. 1324b(a)(3), all applicants may be subject to an export license review process prior to employment.

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Memory Layout Senior Staff Engineer

Memory Layout Senior Staff Engineer