Senior / Lead RTL Design Engineer
Senior / Lead RTL Design Engineer
HuntingCube- Posted 13 hours ago
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Job Description
Job Description
Role Overview Senior / Lead RTL Design Engineer - Semiconductor / VLSI / ASIC Design Senior / Lead RTL Design Engineer Experience: 8–12 Years Domain: Semiconductor / VLSI / ASIC Design Key Skills - Verilog - SystemVerilog - RTL debugging - Clock and reset design - Clock-domain crossing techniques - FIFOs and asynchronous interfaces - State machines and control logic - Pipelining - Bus/interconnect protocols - Lint - CDC/RDC - SDC/timing constraints - Synthesis - Static timing analysis - PCI Express (PCIe) controllers/subsystems - Ethernet controllers/MACs - DDR/LPDDR controllers - DMA engines - AXI/AHB/APB interfaces and SoC interconnects - High-speed interface controller logic - Memory controllers or memory subsystems
Required Skills
[Verilog, SystemVerilog, RTL debugging, Clock and reset design, Clock-domain crossing techniques, FIFOs and asynchronous interfaces, State machines and control logic, Pipelining, Bus/interconnect protocols, Lint, CDC/RDC, SDC/timing constraints, Synthesis, Static timing analysis]
Additional Information
Use public JD while sourcing.
Role Overview Senior / Lead RTL Design Engineer - Semiconductor / VLSI / ASIC Design Senior / Lead RTL Design Engineer Experience: 8–12 Years Domain: Semiconductor / VLSI / ASIC Design Key Skills - Verilog - SystemVerilog - RTL debugging - Clock and reset design - Clock-domain crossing techniques - FIFOs and asynchronous interfaces - State machines and control logic - Pipelining - Bus/interconnect protocols - Lint - CDC/RDC - SDC/timing constraints - Synthesis - Static timing analysis - PCI Express (PCIe) controllers/subsystems - Ethernet controllers/MACs - DDR/LPDDR controllers - DMA engines - AXI/AHB/APB interfaces and SoC interconnects - High-speed interface controller logic - Memory controllers or memory subsystems
Required Skills
[Verilog, SystemVerilog, RTL debugging, Clock and reset design, Clock-domain crossing techniques, FIFOs and asynchronous interfaces, State machines and control logic, Pipelining, Bus/interconnect protocols, Lint, CDC/RDC, SDC/timing constraints, Synthesis, Static timing analysis]
Additional Information
Use public JD while sourcing.
More Info
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Key Skills
Clock and reset design
DDR LPDDR controllers
Ethernet controllers MACs
AXI AHB APB interfaces and SoC interconnects
DMA engines
Memory controllers or memory subsystems
RDC
RTL debugging
SDC timing constraints
State machines and control logic
Clock-domain crossing techniques
PCI Express PCIe controllers subsystems
Bus interconnect protocols
High-speed interface controller logic
FIFOs and asynchronous interfaces
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