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Senior Lead Engineer - RTL

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  • Posted a month ago
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Job Description

Job Requirements

Senior Lead RTL Engineer

  • Design and develop RTL (Verilog/SystemVerilog) for ASIC/SoC
  • Own module-level architecture and micro-architecture definition
  • Work closely with verification, synthesis, and physical design teams
  • Drive RTL quality: lint, CDC, synthesis readiness
  • Support integration and debug of complex SoC designs
  • Mentor junior engineers and guide technical decisions
  • Collaborate with global teams (India/Japan)

Work Experience

  • Strong RTL design (Verilog/SystemVerilog)
  • Good understanding of SoC architecture
  • Experience with synthesis, timing basics (STA awareness)
  • Debug and problem-solving skills
  • Knowledge of low-power / DFT / CDC is a plus

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About Company

Job ID: 150669891

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