Senior Engineer Digital Functional Verification

We are seeking a Senior Engineer for Digital Functional Verification to join our dynamic team in India. The ideal candidate will have extensive experience in designing and implementing verification environments for complex digital systems, ensuring that our products meet the highest standards of quality and performance.

Responsibilities

• Design and implement functional verification test benches for complex digital systems.
• Develop and execute verification plans and strategies to ensure high-quality product delivery.
• Collaborate with hardware and software teams to define test specifications and verification requirements.
• Utilize System Verilog and UVM methodologies for creating robust test environments.
• Perform coverage analysis and debug simulation results to identify and resolve design issues.
• Mentor junior engineers and provide guidance on best practices in functional verification.

Skills and Qualifications

• Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or a related field.
• 6-10 years of experience in digital functional verification.
• Strong proficiency in System Verilog and UVM (Universal Verification Methodology).
• Experience with RTL design and simulation tools (e.g., ModelSim, VCS, QuestaSim).
• Knowledge of digital design concepts and methodologies.
• Familiarity with scripting languages such as Python or Tcl for automation tasks.
• Excellent problem-solving skills and attention to detail.
• Strong communication and teamwork skills.