Senior Engineer Design

In your new role you will:

• Candidate will be responsible for building/maintaining highly configurable and reusable IO Subsystems (Note: An IO Subsystem is a logic IP that processes theIO Pads/IO Ring informationand required logic to allow multiple on-chip peripherals to share the same IOs in aconfigurable manner)
• Candidate will be responsible forRTL design for integration of IOpads into SoC, building the required multiplexing logic and necessary powercontrol signals integration.
• Strong fundamentals in DFT/Fault-grading and/or hands on experience.
• Sound & Practical Written and Verbal Communication Skills.

Your Profile

You are best equipped for this task if you have:

• Must have worked inASIC Design flow, with ASIC experienceof upto 5years.
• Must be strong in scripting using Perl/Python
• Must be familiar withRTL design for ASIC developmentusing Verilog.
• Must be familiar withLINT (LEDA / Spyglass) , Clock-Domain-Crossinganalysis, UPF, MVRC, Synthesis, Timing constraints and debugging STA reports.
• Strong mindset towards automation of repetitive work.
• Strong fundamentals in DFT/Fault-grading and/or hands on experience.
• Sound & Practical Written and Verbal Communication Skills.
• Moderate Individual Contributor with Freedom to Act, Team work and Learn