Senior Digital Design Engineer

Company Description

Chiplogic Technologies is a dynamic IP and Product Engineering Services company established in 2018. With expertise in Semiconductor, Systems, IoT, and AI/ML, Chiplogic delivers high-quality and dependable technical services. The company specializes in offering full turnkey semiconductor design and system solutions, from concept to silicon, and IoT-based solutions utilizing its proprietary VISARD™ (Video Synthesis and Real-time Dynamics) framework. Chiplogic is dedicated to delivering innovative technologies and solutions across a range of emerging industries.

Role Description

We are looking for an experienced and highly motivated Senior Digital Design Engineer to join our growing VLSI/ASIC design team. The ideal candidate should have strong expertise in RTL design, micro-architecture development, and digital design implementation for complex SOC/IP projects.

• Develop RTL designs using Verilog/SystemVerilog for complex digital blocks and SOC subsystems.
• Work on micro-architecture definition and design specifications.
• Perform design analysis, linting, CDC checks, and low-power design implementation.
• Collaborate closely with Verification, Physical Design, DFT, and Architecture teams.
• Debug and resolve design and integration issues during various stages of the project lifecycle.
• Ensure high-quality and reusable RTL coding practices.
• Participate in design reviews and technical discussions with internal and external stakeholders.

• Strong experience in RTL Design using Verilog/SystemVerilog.
• Good understanding of SOC architecture and digital design concepts.
• Hands-on experience in synthesis, lint, CDC, and timing-aware design practices.
• Knowledge of AMBA protocols such as AXI, AHB, APB is preferred.
• Experience working on high-speed interfaces and low-power design techniques is an advantage.
• Strong debugging and problem-solving skills.
• Familiarity with ASIC design flow and EDA tools.

• Bachelor's or Master's degree in Electronics/Electrical Engineering or related field.
• Experience in semiconductor/VLSI domain with successful tape-out exposure preferred.

• Immediate joiners preferred.
• Candidates should be open for face-to-face interviews.