You Are:

As an ideal candidate for the ASIC Digital Design Engineer, Senior role, you are a highly motivated and innovative individual with a deep understanding of ASIC development flow. You possess a strong theoretical and practical background in high-speed serializer and data recovery circuits. You are someone who thrives in dynamic environments and embraces the challenges that come with constant technological changes. You are self-motivated, proactive, and able to balance good design quality with tight deadlines. Your excellent communication skills enable you to interact seamlessly with different design groups and customer support teams. You are known for your ability to resolve issues creatively and exercise independent judgment in selecting methods and techniques to obtain solutions. You are a team player who can produce excellent results both as an individual and as part of a team.

What You ll Be Doing:

Developing and verifying digital designs for next-generation NRZ and PAM-based SerDes products.
Running lint/cdc/rdc checks and synthesis flow.
Working with Verilog and VCS to ensure design accuracy.
Defining synthesis design constraints and resolving STA issues.
Collaborating with mixed-signal engineers to deliver high-end mixed-signal designs from specification development to functional and performance tests.
Interacting with Application Engineers for customer support and resolving technical issues with Analog and P&R teams.

The Impact You Will Have:

Contributing to the development of cutting-edge SerDes products that lead the industry.
Enhancing the performance, power, and size efficiency of our silicon IP offerings.
Enabling rapid market entry for differentiated products with reduced risk.
Driving innovation in high-speed digital design and data recovery circuits.
Supporting the creation of high-performance silicon chips and software content.
Collaborating with a world-class team to solve complex design challenges.

What You ll Need:

BSEE or MSEE with a minimum of 2 years of experience in digital design and front-end flows.
Proficiency in running lint/cdc/rdc checks and synthesis flow.
Experience with Verilog and VCS.
Knowledge of digital design methodologies, DFT insertion, synthesis constraints, and flows.
Scripting experience in Shell, Perl, Python, and TCL (preferred).

Who You Are:

Excellent communicator with the ability to interact with diverse teams.
Self-motivated and proactive, with a strong attention to detail.
A creative problem-solver who can think independently.
Capable of working under tight deadlines while maintaining high-quality standards.
A team player who can contribute effectively both individually and collaboratively.