Senior DFT Design Engineer

KEY RESPONSIBILITIES:

• Implementation and verification of DFT features like SCAN, MBIST, LBIST and JTAG
• Support Spyglass-DFTDRC debug and coverage correlation
• Scan insertion and ATPG pattern generation
• ATPG patterns verification with gate-level simulation
• Test coverage and test cost reduction analysis
• Post silicon support to ensure successful bring up and enhance yield learning

PREFERRED EXPERIENCE:

• Experience in scan-stitching; and has good knowledge of scan-stitching related concepts
• Exposure to MBIST/BISR implementation and with the Tessent flow of mbist-insertion
• Excellent hands-on ATPG; and is we'll conversed with the files required to run ATPG
• Knowledge/experience with Tessent ATPG (mentor) is a plus
• Knowledge on Spyglass-DFT
• Excellent hands-on debug skills and scripting skills are critical
• Knowledge on automation scripts like TCL/AWK/SED is a plus
• Understands the basics of JTAG
• Experience with post-silicon bring up is a plus

ACADEMIC CREDENTIALS:

• Bachelors degree w/7+ years or Masters degree w/5+ years in Electronics engineering/Electrical Engineering