Soc Architecture, Tcl, Python, Perl, HDLs, MBIST, ATPG flow implementation, UPF, Cadence digital implementation tools, DFT architecture definition, Tempus, CPF, Scan, Genus, tessent DFT, JTAG boundary scan

Python, Perl, Logic Design, Profiling Tools, Uvm, Post Silicon Testing, SV, Constrained random testing, Architecture Verification, DFT Engineering, Coverage metrics

Verilog, Jtag, Dft, MBIST, IEEE1500, IEEE1687, ATPG, Cadence

scan compression, BSCAN, Simulation, MBIST, DFT insertion, ATPG, LBIST, pattern generation, IJTAG

Scan, HDLs, MBIST, DFT architecture definition, Tempus, ATPG flow implementation, scripting skills in Perl, Genus, tessent DFT, JTAG boundary scan, Cadence digital implementation tools

.V, ijtag - P1687, Scripting, Shell, Tcl, ICL, PDL Writing, STIL, SVF, Tessent shell, SSN, Jtag 1149.1-2013, Tessent tool, Debug patterns, SSH architecture, Debug protocols, TestKompress