Senior Design Verification Engineers

Senior GLS Verification Engineers

Experience : 7 years

Location : Bangalore

We are working with a huge ASIC that requires people solid experience in gate level verification.

We are looking for candidates who during multiple projects have gained experience in:

Basic necessities:

-What it takes to bring up a gate level simulation from scratch

o Understanding of the differences in setting up a testbench for GLS compared to RTL simulation.

Debug the boot process

i.e. not just experience of running tests in an environment prepared by others.

-Solid experience of debugging x-propagations using waveforms.

Highly desired:

Understand the challenges of GLS of large designs requiring say at least 100GB of simulation memory ( our design is about 1.3TB)

Knowledge of XPROP RTL simulations

Interested,please drop your updated resume to [Confidential Information]