Senior Design Verification Engineer

Company Description

SmartSoC Solutions is a leading Product Engineering Services company specializing in Semiconductor Design Services, Embedded Systems, Digital Solutions, Artificial Intelligence, Machine Learning, IoT, Networking, and Robotics. With a strong focus on empowering clients to design and build next-generation products, SmartSoC Services spans diverse industries such as Semiconductor, Consumer Electronics, Automotive, and more. The company operates globally across countries such as India, the USA, Sweden, and Canada, with a team of over 1,250 skilled engineers and scientists. Known for its innovative approach and comprehensive solutions, SmartSoC is committed to delivering top-quality services from concept to production.

We are looking for a Design Verification Engineer with strong hands-on experience in SystemVerilog, UVM, and industry-standard interconnect and memory protocols to verify complex ASIC/SoC designs.

• Develop and maintain SystemVerilog/UVM-based verification environments
• Create verification plans, testbenches, sequences, scoreboards, and coverage models
• Perform block-level and SoC-level verification
• Verify designs using standard protocols including: AMBA (AXI, AHB, APB), PCIe, Ethernet, DDR
• Debug functional issues and collaborate closely with design and architecture teams
• Drive functional and code coverage closure
• Support regression, gate-level simulations, and verification sign-off

• 5+ years of experience in Design Verification
• Strong expertise in SystemVerilog and UVM
• Hands-on experience with AMBA protocols
• Working knowledge of PCIe, Ethernet, and DDR protocols
• Solid understanding of digital design fundamentals and verification methodologies
• Experience with simulators, waveform debugging, and coverage tools

• SoC-level verification experience
• Experience with protocol VIPs
• Scripting skills (Python, Perl, Shell)
• Exposure to low-power or formal verification