Skill: Senior DV Engineer
Exp: 5-10 Years
Location: Singapore
Notice: Immediate - 30 days
JD:
- Test bench development and debug
- Strong Expertise in Digital, Verilog & SV.
- UVM/C based test case development and debug.
- Power aware test case development and debug
- External/Internal VIP based test development and debug.
- Mixed-signal block modelling and RNM based testing.
- Coverage analysis (code, functional, assertion)
- Verification plan reviews, Verification reviews
- Back-annotated netlist simulation execution and debug
- Debug failing cases & Coverage improvements.
