Pcie, System Verilog, Python, Systemc, Hybrid test benches, MDV, DV signoffs, SV, Uvm, UCIe, Axi, CDV

Fpga, Perl, Python, Emulation, RTL, Uvm, systemverilog

Usb, Tcl, Ethernet, Python, Perl, Pcie, DDR, systemverilog, Uvm, coverage-driven verification, AMBA, digital design RTL understanding, SVA, MIPI

Vcs, Questa, SVA, Uvm, systemverilog, functional coverage assertions

test environments , SystemVerilog Assertions (SVA, Gate-Level Simulation (GLS, Test Cases, Uvm, formal verification, Coverage measures, Constrained-random verification environments, systemverilog, Low power debug, Verification methodologies, Formal tools, Verification test benches

Verilog, Scripting Languages, Verification Tools, VHDL, Uvm, formal verification, Simulators

Perl, Python, Tcl, DisplayPort, HDMI, MIPI DSI, Uvm, systemverilog

C, Perl, Python, Low power verification methods, FPGA emulator software environments, Emulation platforms, Uvm, systemverilog, Industry standard I/O interfaces, AMBA bus protocols, RTL development environments, Baremetal processor environments, Formal verification methods, UPF based low power verification, Transaction level modeling

Tcl, Python, Perl, Shell, Debugging RTL verification issues, Assertions SVA, Functional Verification, UVM methodology, systemverilog, Coverage-driven verification