Senior Design Verification Engineer

Silicon Patterns seeks Design Verification Engineers with 5+ years,

Location: Bangalore,

Skills: DDR

Key Responsibilities

• Develop and maintain UVM-based testbenches for DDR IP and SoC-level verification, including constrained-random stimulus, functional coverage, and assertions.
• Debug verification failures, collaborate with design teams on protocol compliance (e.g., DDR timing, memory controllers), and ensure first-pass silicon success.
• Lead or contribute to test plans, coverage closure, and emulation flows for high-performance computing projects.

Required Skills

• 5-10+ years in design verification with hands-on DDR expertise; proficiency in SystemVerilog, UVM, and protocols like PCIe, Ethernet.
• Experience with verification tools (e.g., Questa, VCS), coverage-driven methodologies, and scripting (Perl/Python).
• Strong problem-solving for IP/SoC blocks in domains like AI/ML, automotive, or IoT.

Company Overview

Silicon Patterns is a specialized engineering services company with expertise in pre-silicon and post-silicon design and verification. Headquartered in Hyderabad,

with offices in Bangalore, Raipur, and support teams in Malaysia, we cater to global clients in Wireless, IoT, and Automotive domains.Our solutions cover RTL Design,

SystemC Modeling, Emulation, Design Verification, and Pre- & Post-silicon Validation. We leverage cutting-edge technologies, including AI/ML, GenAI/LLMs,

HBM3/3E workloads, and edge computing, to drive innovation and efficiency. At Silicon Patterns, we value technical excellence and support a healthy work-life balance for our team members.