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Senior Design Verification Engineer
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L&T Technologies (LTTS) is hiring for Design Verification Engineers with 5+ Years of experience ::
Job Location : Bangalore
Please find the detailed job description below ::
Experience in development of UVM based verification environments from scratch.
Experience with Design verification of ta-center applications like Video, AI/ML and Networking designs.
Experience in Mercurial (Hg), Git or SVN. Experience with low power design.
Experience working across and building relationships with cross-functional design, model, and emulation teams.
Strong in Funmentals, Digitial Concepts, Debugging
Low Power and GLS Simulations will be plus
Job ID: 153641619
Skills:
Usb, Mercurial, Svn, DDR, Git, Perl, Pcie, Ethernet, Python, Tcl, UVM methodology, AMBA, SoC level verification, UVM based verification environments, Design Verification infrastructure
Skills:
Perl, Vcs, Python, Tcl, Verdi, Questa, Uvm, systemverilog
Skills:
Vcs, functional coverage assertions, Questa, Uvm, SVA, systemverilog
Skills:
Keysight, Exercisers, LeCroy, PIPE Interface verification, Uvm, PCIe Protocol Gen5, systemverilog, Protocol Analyzers
Skills:
Tcl, Python, Perl, Shell, Debugging RTL verification issues, Assertions SVA, Functional Verification, UVM methodology, systemverilog, Coverage-driven verification
