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Role - Senior Design Verification Engineer
Experience - 7+years
Location - Bangalore, Hyderabad, Pune and Kochi
Notice Period - Immediate to 60days
JD Design Verification
• Understanding the business requirements and functional specifications of the IPs, subsystems and SOC
• Creating Verification Environment Architecture document
• Reviewing and Revising: working towards meeting agreed upon acceptance criteria
• Developing code in System Verilog, UVM (Universal Verification Methodology), C for Unit, Subsystem and SOC level verification
• Performing RTL simulations using Synopsys and Cadence simulators
• Debugging and resolving problems found by simulations .Performance test plan development and maintenance
• Development of transactors, monitors and models for performance verification.
• Implement performance verification flow including monitoring, synchronization, reporting and self-checking mechanisms
• Provide full report of performance metrics and bottlenecks
• Tracking tickets and code releases using Bug Tracking tool and GIT
• Performing UPF (Unified Power Format) based Power Aware simulations
• Coding of Assertion and Functional Coverage bins in SVA (System Verilog Assertions)
• Code & Functional Coverage Closure
Performing Gate Level simulations .Preparing and conducting reviews of Verification Sign-off documents to ensure SOC tape-out quality
Job ID: 145189713
Skills:
Vcs, Git, Pcie, Ethernet, System Verilog, low-power verification techniques, cdc, Uvm, UPF, C Language, Axi, level shifter implementation, AMBA, FIFOs, APB, Questa, RISC-V CPU subsystems, clock reset architectures, power management strategies, AHB
Skills:
scoreboard , System Verilog, script development, Uvm, verification closure, verification environment, testbench components, interface agents
Skills:
analog circuits , Fpga, Logic Design, Verilog, Sta, Scan Insertion, Power product design, Uvm, Synthesis scripts, ATPG generation, Regression frameworks, Synthesis, formal verification, Micro-architecture, ABV, RTL Coding, Timing Constraints, Functional Verification, System-Verilog, Digital Verification, Timing Analysis
Skills:
DDR, Pcie, Uart, I2c, Axi, IP verification, FPGA-based verification, APB, Uvm, C-based tests, systemverilog
Skills:
code coverage , System Verilog, Cover groups, Functional coverage, Assertions, DDR4, Uvm, DIMM, DDR5
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