Senior Design Verification Engineer

Company Description

Chiplogic Technologies, established in 2018, is an IP and Product Engineering Services company specializing in Semiconductor, Systems, IoT, and AI/ML domains. The company offers comprehensive services, from semiconductor design and system solutions to Proof of Concept (POCs) and IoT final system solutions. Leveraging its proprietary VISARD™ framework (Video Synthesis And Real-time Dynamics), Chiplogic delivers reliable and innovative solutions. With a focus on quality and technical excellence, Chiplogic has established itself as a trusted partner in cutting-edge technology development.

Job Description:

We are looking for a highly skilled Senior Design Verification Engineer with 5+ years of experience in verifying complex SoC/IP designs, with strong expertise in PCIe (Peripheral Component Interconnect Express) protocol. The ideal candidate will be responsible for developing and executing verification strategies to ensure high-quality silicon for next-generation semiconductor products.

Key Responsibilities:

• Develop and execute verification plans for complex IP/SoC designs.
• Build and maintain SystemVerilog/UVM based verification environments.
• Perform PCIe protocol verification including LTSSM, link training, configuration space, and transaction layer validation.
• Develop test benches, assertions, and functional coverage models.
• Debug simulation failures and collaborate with design teams to resolve issues.
• Perform coverage analysis and ensure verification closure.
• Work with VIPs, scoreboards, monitors, and checkers for efficient verification.
• Participate in design reviews and provide feedback on verification strategies.

Required Skills:

• Strong expertise in SystemVerilog and UVM methodology.
• Experience in PCIe protocol verification (Gen3/Gen4/Gen5 preferred).
• Good understanding of digital design fundamentals and computer architecture.
• Experience in functional coverage, assertions (SVA), and constrained random verification.
• Hands-on experience with EDA tools (Cadence / Synopsys / Mentor Graphics).
• Knowledge of debugging simulation issues and waveform analysis.
• Good scripting knowledge in Python/Perl/Shell is a plus.

Preferred Qualifications:

• Experience in SoC verification and IP integration.
• Knowledge of other protocols like AXI, AHB, APB is an advantage.
• Exposure to emulation or FPGA-based verification is a plus.

Education:

• Bachelor's or Master's degree in Electronics / Electrical Engineering / VLSI / Computer Engineering.