Senior Design Verification Engineer

Role Description This is a full-time, on-site Senior Design Verification Engineer role based in Bengaluru. The role involves planning and executing verification strategies for complex IP, subsystem, and SoC designs, including testbench architecture, testcase development, and coverage closure. The Senior Design Verification Engineer will write and review verification plans, develop and maintain UVM or similar environments, run simulations, analyze results, and drive root-cause analysis for functional issues. The role includes close collaboration with RTL design, architecture, and formal verification teams to refine specifications, improve design quality, and ensure robust sign-off criteria. The individual will mentor junior engineers, contribute to methodology improvements, and support project execution timelines and quality metrics.

Qualifications

• Strong functional verification skills, including experience with testbench development, constrained random testing, coverage analysis, and simulation-based verification.
• Proficiency in formal verification and related methodologies for proving correctness and enhancing overall verification quality.
• Solid RTL design skills, with the ability to understand, review, and debug hardware description language code (e.g., Verilog/SystemVerilog).
• Good understanding of computer architecture concepts, including pipelines, caches, memory subsystems, and bus/interconnect protocols.
• Advanced debugging skills using waveforms, logs, assertions, and standard EDA tools to identify and resolve complex design and verification issues.
• Hands-on experience with industry-standard verification tools and flows (e.g., simulators, coverage tools, lint, CDC), and UVM or similar frameworks.
• Bachelor's or Master's degree in Electrical Engineering, Electronics, Computer Engineering, or a related discipline, or equivalent practical experience.
• Experience in verification of CPU/GPU, high