Usb, DDR, Shell, Perl, Ethernet, Python, Emulation, UVM methodology, high-speed interfaces PCIe, systemverilog, scoreboards, industry-standard simulators and tools, formal verification, ASIC SoC architecture, functional coverage assertions, debugging skills, low-power verification UPF, SVA

Unix, Makefile, Shell, Configuration Management, PERL, System Verilog, Python, Verification dashboarding tools, ARM CPU, PCI Express, Uvm, AMBA bus protocols, Ethernet bus protocols

code coverage , System Verilog, Cover groups, Functional coverage, Assertions, DDR4, Uvm, DIMM, DDR5

AMBA5 protocols (AXI5/ACE5/CHI), Cache coherency protocols (CHI, CXL), SystemVerilog UVM-based testbench development, Ace, CCIX, Functional coverage

Test Plan Creation, Debugging, Python, Perl, VIP integration, testbench architecture, Uvm, verification methodologies, scoreboarding, systemverilog, coverage-driven verification, execution and review, assertions, regression management, debug flows, functional coverage

Soc Architecture, Shell, Perl, System Verilog, Python, Cadence Xcelium, Simulation Tools, Uvm, Synopsys VCS, digital design concepts, Axi, AMBA, APB, AHB, debugging using waveforms and logs