Python, Jasper, Perl, functional coverage, SVA, Uvm, VC Formal, verification methodologies, systemverilog, Asic verification, Cadence IEV, Synopsys Magellan

Test Plan Creation, Debugging, Python, Perl, VIP integration, testbench architecture, Uvm, verification methodologies, scoreboarding, systemverilog, coverage-driven verification, execution and review, assertions, regression management, debug flows, functional coverage

Tcl, Python, Perl, Shell, Debugging RTL verification issues, Assertions SVA, Functional Verification, UVM methodology, systemverilog, Coverage-driven verification

Verilog, Tcl, Python, Perl, Uvm, VHDL, systemverilog

Tcl, Python, Perl, systemverilog, Functional Verification, UVM methodology, High-speed networking interfaces, Coverage-driven verification, Ethernet IPs, Emulation platforms or FPGA prototyping

Verilog, Python, Perl, Synopsys VCS, VHDL, Uvm, Modelsim, Cadence Incisive