Position - Senior DV Engineer
Location - Bengaluru, Hyderabad, pune
Manage SOC Design Verification efforts for complex projects, ensuring the successful execution of verification plans.
About the Role
Develop and implement comprehensive verification strategies, test plans, and test benches for high-speed SOCs, including low-speed peripherals like I2C/I3C, SPI, UART, GPIO, QSPI, and high-speed protocols like PCIe, Ethernet, CXL, MIPI, DDR and HBM.
Responsibilities
- Manage SOC Design Verification efforts for complex projects.
- Ensure the successful execution of verification plans.
- Develop and implement comprehensive verification strategies.
- Create test plans and test benches for high-speed SOCs.
- Work with low-speed peripherals like I2C/I3C, SPI, UART, GPIO, QSPI.
- Handle high-speed protocols like PCIe, Ethernet, CXL, MIPI, DDR, and HBM.
- Experience on Gate-level simulations, and power-aware verification using Xprop and UPF is an added advantage.
- Analyze and implement System Verilog assertions and coverage (code, toggle, functional).
- Demonstrate dedication, hard work, and commitment to achieving project goals and deadlines.
Qualifications
Education details -engineering - equivalent
Required Skills
- Experience on Gate-level simulations.
- Power-aware verification using Xprop and UPF.
- System Verilog assertions and coverage analysis.
Preferred Skills
- Dedication and commitment to project goals.
- Ability to work under deadlines.
Pay range and compensation package
- Pay range or salary or compensation
Equal Opportunity Statement
Include a statement on commitment to diversity and inclusivity.
