Develop SoC-level verification plans and strategies based on architecture, interconnect, and subsystem specifications.
Architect UVM/SystemVerilogbased testbenches for complex SoC environments, including integration of multiple IPs and verification components.
Create directed and constrained-random tests to verify SoC features such as interconnect protocols, power/clock/reset domains, security, coherency, and low-power flows.
Drive functional, code, and system-level coverage closure; identify gaps and ensure verification completeness.
Debug complex SoC interactions using waveforms and logs; collaborate closely with RTL, firmware, and validation teams to resolve issues.
Manage regressions, automation flows, and infrastructure for large-scale SoC simulations.
Lead feature-level verification efforts, mentor junior DV engineers, and review testbench code.
Deliver clear documentation, verification reports, and ensure SoC readiness for tape-out.
