Senior Design Verification Engineer

• Verification of complex ASIC chips and sub-systems using leading edge verification methodologies.
• Create verification plans for blocks and full chip by developing a thorough understanding of the design under test.
• Employ UVM/SystemVerilog based verification methodologies and use assertions, functional/code coverage, formal verification etc to reach verification goals.
• Develop reference models or scoreboards for checking design features.
• Contribute and influence the decisions on methodologies to be adopted for the verification.
• Gate level simulations and debug of large digital blocks and full-chip ASICs
• Support post-silicon validation activities of the products working with design, applications and test teams

Job Requirements:

• Bachelors or masters degree in Electrical or Computer Engineering with at least 3 years of experience in Digital Verification.
• Proficient in Verilog, System Verilog, UVM, object-oriented programming, scripting and automation with Perl or Python.
• Firm understanding of constrained random functional verification, coverage, and assertions.
• Experience with test plan development and development of verification environments from ground up.
• Experience with verification of complex blocks, regressions and coverage closure.
• Experience with gate level simulations and debug.
• Excellent debugging, analytical and problem-solving skills.
• Strong inter-personal, teamwork and communication skills.
• Expected to be highly independent, proactive and result-oriented to achieve verification goals.

Preferred qualifications:

• Knowledge of I2C, UART, SPI, Ethernet, Video (DisplayPort, CSI/DSI), PCIe and Audio I2S interfaces.
• Experience with lab silicon bring-up, validation and production test support