Senior Design Verification Engineer
Senior Design Verification Engineer
ALTEN Calsoft LabsEarly Applicant
- Posted a month ago
- Be among the first 10 applicants
Job Description
Faulsim-Engineers
Experience : 4-7 years
Good Experience on Semiconductor/VLSI Design verification IP's.
Experience with ISO 26262 is plus
Must have Faultsim experience
Z01X tool experience and any equivalent tool
Can consider GLS experience with good verification knowledge.
Interested,please share your updated resume to [Confidential Information]
More Info
About Company
Skills:
SystemVerilog Assertions (SVA), test environments , Gate-Level Simulation (GLS), Test Cases, Low power debug, Constrained-random verification environments, Uvm, systemverilog, Verification test benches, Formal tools, Verification methodologies, Coverage measures, formal verification
Skills:
Unreachability (UNR) analysis, RTL and Gate-Level Simulations (GLS), Formal Property Verification (FPV), Reset Domain Crossing (RDC) assertions, SystemVerilog (SV), Shell scripting, UVM methodologies, Connectivity checks, Power-aware simulations