SystemVerilog Assertions (SVA), test environments , Gate-Level Simulation (GLS), Test Cases, Low power debug, Constrained-random verification environments, Uvm, systemverilog, Verification test benches, Formal tools, Verification methodologies, Coverage measures, formal verification

Unreachability (UNR) analysis, RTL and Gate-Level Simulations (GLS), Formal Property Verification (FPV), Reset Domain Crossing (RDC) assertions, SystemVerilog (SV), Shell scripting, UVM methodologies, Connectivity checks, Power-aware simulations