IP Verification Engineer UVM verification
Experience : 5-7 years
Location : Hyderabad
- System Verilog based UVM Functional verification, Behavioral modelling of functional blocks.
- System level performance verification, traffic patterns, bandwidth & latency analysis.
- Expertise in AXI4 bus protocol. Experience in Network On Chip (NOC) protocol.
- Experience in multi-master, multi-slave AXI4 use-case configurations. Knowledge of DRAM memory controllers.
- Develop and execute testbenches to validate the functionality and correctness of models, as well as participate in system-level testing and debugging.
- Setup verification environment and bring up simulations with various simulations such as VCS / Questa / Xcellium / Riviera
- SV/UVM Functional verification
- Expertise in Vivado for simulation debugs
Interested,please share your updated resume to [Confidential Information]
