Senior Design Engineer
Senior Design Engineer
Intel CorporationThis job is no longer accepting applications
Job Description
In this position, the candidate will be responsible for design of soft IP cores for Intel's next generation chips (including SOCs) for the different market segments.
The engineer will be responsible for the execution and quality of at least 2 IPs and will sign off all design checks and interact with SOC for all integration issues
Qualification
Master of Science (or a Master of Technology) degree in Electrical Engineering with more than 12 years of relevant industry experience or a Bachelor of Science (Bachelor of Technology) degree in Electrical Engineering with more than 14 years of relevant industry experience.
Experience : Relevant ASIC design/validation experience in front end processes including RTL development, functional and performance verification
Expertise in design, development and integration of design blocks (IP) for system-on-chip (SoC) components
Expertise in verilog and system verilog based logic design
Experience in all design tools like linting, DC, CDC, LEC
Experience in one/more of the following areas PCI_Express, USB, SATA, SDIO,MIPI and /or AMBA standards (OCP, AXI, AHB etc..)
Knowledge of SVA
Knowledge of RAS domain is a bonus
Knowledge of considerations for performance, power and cost optimization is desirable
The Data Center & Artificial Intelligence Group (DCAI) is at the heart of Intel's transformation from a PC company to a company that runs the cloud and billions of smart, connected computing devices. The data center is the underpinning for every data-driven service, from artificial intelligence to 5G to high-performance computing, and DCG delivers the products and technologies—spanning software, processors, storage, I/O, and networking solutions—that fuel cloud, communications, enterprise, and government data centers around the world.All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.It has come to our notice that some people have received fake job interview letters ostensibly issued by Intel, inviting them to attend interviews in Intel's offices for various positions and further requiring them to deposit money to be eligible for the interviews. We wish to bring to your notice that these letters are not issued by Intel or any of its authorized representatives. Hiring at Intel is based purely on merit and Intel does not ask or require candidates to deposit any money. We would urge people interested in working for Intel, to apply directly at https://jobs.intel.com/ and not fall prey to unscrupulous elements.This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change.We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock, bonuses, as well as, benefit programs which include health, retirement, and vacation. Find more information about all of our Amazing Benefits here.
The engineer will be responsible for the execution and quality of at least 2 IPs and will sign off all design checks and interact with SOC for all integration issues
Qualification
Master of Science (or a Master of Technology) degree in Electrical Engineering with more than 12 years of relevant industry experience or a Bachelor of Science (Bachelor of Technology) degree in Electrical Engineering with more than 14 years of relevant industry experience.
Experience : Relevant ASIC design/validation experience in front end processes including RTL development, functional and performance verification
Expertise in design, development and integration of design blocks (IP) for system-on-chip (SoC) components
Expertise in verilog and system verilog based logic design
Experience in all design tools like linting, DC, CDC, LEC
Experience in one/more of the following areas PCI_Express, USB, SATA, SDIO,MIPI and /or AMBA standards (OCP, AXI, AHB etc..)
Knowledge of SVA
Knowledge of RAS domain is a bonus
Knowledge of considerations for performance, power and cost optimization is desirable
The Data Center & Artificial Intelligence Group (DCAI) is at the heart of Intel's transformation from a PC company to a company that runs the cloud and billions of smart, connected computing devices. The data center is the underpinning for every data-driven service, from artificial intelligence to 5G to high-performance computing, and DCG delivers the products and technologies—spanning software, processors, storage, I/O, and networking solutions—that fuel cloud, communications, enterprise, and government data centers around the world.All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.It has come to our notice that some people have received fake job interview letters ostensibly issued by Intel, inviting them to attend interviews in Intel's offices for various positions and further requiring them to deposit money to be eligible for the interviews. We wish to bring to your notice that these letters are not issued by Intel or any of its authorized representatives. Hiring at Intel is based purely on merit and Intel does not ask or require candidates to deposit any money. We would urge people interested in working for Intel, to apply directly at https://jobs.intel.com/ and not fall prey to unscrupulous elements.This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change.We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock, bonuses, as well as, benefit programs which include health, retirement, and vacation. Find more information about all of our Amazing Benefits here.
More Info
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Key Skills
integration of design blocks
MIPI
linting
AMBA standards
ASIC design validation
About Company
Skills:
micro architecture , X86, Computer Architecture, Arm, Processor Asic design flow, ECO bring up, Design Verification, Fetch Decode Load-Store, high performance microprocessor architecture, L1 L2 caches, Coherency, CPU microarchitecture, Memory Design, Processor Instruction set architecture, PD synthesis, Rtl Design, Prefetch, Memory Ordering Rules, PPA optimization, Power
Skills:
altium , thermal management , ltspice , MATLAB, ALLEGRO, surge reliability, Si SiC devices, Reliability, environmental qualification, Simulink, gate drives, Psim, lithium-ion batteries, Pspice, magnetics, sensing isolation protection, EMC safety, grid-following operation, DC-link design, grid interacting ESS, UL IEC standards, PLECS, Cadence OrCAD, BMS integration
Skills:
Pcie, System Verilog, Python, Systemc, Hybrid test benches, MDV, DV signoffs, SV, Uvm, UCIe, Axi, CDV
Skills:
clocking , Verilog, EDA tools for synthesis, LINT, Use of AI for design, cdc, SoC-level design and integration, Synthesis flows, Rtl Design, spyglass, VHDL, Verification methodologies, RDC, Digital design principles, Resets, Timing Constraints, Micro-architecture design, Low-power design techniques, Timing Analysis
Skills:
Perl, Verilog, Python, Makefiles, RTL Build flows, SoC Clocks, System-Verilog, Synthesis, RST Debug architecture