micro architecture , X86, Computer Architecture, Arm, Processor Asic design flow, ECO bring up, Design Verification, Fetch Decode Load-Store, high performance microprocessor architecture, L1 L2 caches, Coherency, CPU microarchitecture, Memory Design, Processor Instruction set architecture, PD synthesis, Rtl Design, Prefetch, Memory Ordering Rules, PPA optimization, Power

altium , thermal management , ltspice , MATLAB, ALLEGRO, surge reliability, Si SiC devices, Reliability, environmental qualification, Simulink, gate drives, Psim, lithium-ion batteries, Pspice, magnetics, sensing isolation protection, EMC safety, grid-following operation, DC-link design, grid interacting ESS, UL IEC standards, PLECS, Cadence OrCAD, BMS integration

Pcie, System Verilog, Python, Systemc, Hybrid test benches, MDV, DV signoffs, SV, Uvm, UCIe, Axi, CDV

clocking , Verilog, EDA tools for synthesis, LINT, Use of AI for design, cdc, SoC-level design and integration, Synthesis flows, Rtl Design, spyglass, VHDL, Verification methodologies, RDC, Digital design principles, Resets, Timing Constraints, Micro-architecture design, Low-power design techniques, Timing Analysis

Perl, Verilog, Python, Makefiles, RTL Build flows, SoC Clocks, System-Verilog, Synthesis, RST Debug architecture

Materials and Manufacturing processes, Aerospace UAS design and development, mechanisms, Regulatory compliance and standards in the aerospace industry, Structure Design

C, Perl, Python, Low power verification methods, FPGA emulator software environments, Emulation platforms, Uvm, systemverilog, Industry standard I/O interfaces, AMBA bus protocols, RTL development environments, Baremetal processor environments, Formal verification methods, UPF based low power verification, Transaction level modeling