Senior Design Engineer
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Job Summary:
We are seeking a highly skilled Design Verification Engineer (DV) to join our growing team and play a vital role in ensuring the quality and functionality of our advanced ASICs and SoCs. This position requires a strong foundation in verification methodologies and the ability to handle complex verification tasks. You will be instrumental in developing robust verification plans and environments to guarantee the success of our next-generation integrated circuits.
Responsibilities
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Qualification
am
Benefi
Job ID: 151077061
Skills:
Verilog Hdl, Writing design micro-architecture specifications, LINT, Power management and low-power design techniques, Design for IPs, cdc, Hands-on RTL development expertise, Power checks, Static checks, digital hardware design, RDC, Synthesis timing analysis, Clock power domain implementations
Skills:
telemetry , Verilog, System Verilog, Debug, secure MMIO access-control, AXI-Lite, transaction error handling, Axi, APB, EDA Tools, parity ECC schemes, RTL Coding, privilege-based filtering, firewall logic, RAS concepts
Skills:
Perl, Python, Tcl, Clock domain partitioning, Power integrity and power-aware physical implementation, Block and subsystem-level physical design flows, primetime, Fusion Compiler, Clock gating, Congestion analysis and resolution, Clock tree architecture, Tempus, Cadence Innovus, Skew management, Certus, Synopsys ICC2, Timing closure and constraint management
Skills:
Keysight, Exercisers, LeCroy, PIPE Interface verification, Uvm, PCIe Protocol Gen5, systemverilog, Protocol Analyzers
Skills:
Fpga, Perl, Python, Emulation, RTL, Uvm, systemverilog
