Verilog Hdl, Writing design micro-architecture specifications, LINT, Power management and low-power design techniques, Design for IPs, cdc, Hands-on RTL development expertise, Power checks, Static checks, digital hardware design, RDC, Synthesis timing analysis, Clock power domain implementations

telemetry , Verilog, System Verilog, Debug, secure MMIO access-control, AXI-Lite, transaction error handling, Axi, APB, EDA Tools, parity ECC schemes, RTL Coding, privilege-based filtering, firewall logic, RAS concepts

Perl, Python, Tcl, Clock domain partitioning, Power integrity and power-aware physical implementation, Block and subsystem-level physical design flows, primetime, Fusion Compiler, Clock gating, Congestion analysis and resolution, Clock tree architecture, Tempus, Cadence Innovus, Skew management, Certus, Synopsys ICC2, Timing closure and constraint management

Keysight, Exercisers, LeCroy, PIPE Interface verification, Uvm, PCIe Protocol Gen5, systemverilog, Protocol Analyzers

Fpga, Perl, Python, Emulation, RTL, Uvm, systemverilog

Rtos, Embedded Linux, Uart, Spi, Git, Ipc Mechanisms, I2c, C Programming, Python, BACnet, Modbus, Linux process management

C, Pcie, Ethernet, SV, CXL, Uvm, UCIe, systemverilog

Vcs, functional coverage assertions, Questa, Uvm, SVA, systemverilog

Verilog, multi-clock designs, Synthesis, formal verification, ECO fixes, SoC clocking reset architecture, Logic design RTL coding, SoC design and integration, Timing Concepts, asynchronous interfaces, System-Verilog