Static checks (Lint, rtl development , Power checks), Clock power domain implementations, Verilog Hdl, Synthesis timing analysis, Power management and low-power design techniques, digital hardware design, ARM System Architectures, DFT and physical implementation flows, Micro-architecture specifications, ARM-based designs, cdc, RDC, Advanced synthesis checks

telemetry , Verilog, System Verilog, Debug, secure MMIO access-control, AXI-Lite, transaction error handling, Axi, APB, EDA Tools, parity ECC schemes, RTL Coding, privilege-based filtering, firewall logic, RAS concepts, Mentor Graphics, Cadence, Synopsys

power integrity , Perl, Python, Tcl, physical design sign-off, static dynamic IR drop, physical ECOs, Cadence Voltus, electromigration, power-grid optimization, PG strengthening, Ansys RedHawk, EM IR analysis, vectorless EM IR analysis

Pcie, System Verilog, Python, Systemc, Hybrid test benches, MDV, DV signoffs, SV, Uvm, UCIe, Axi, CDV

Design Verification, Debugging RTL Verilog designs

layout verification , very large scale integration (VLSI) design, system on a chip (SoC), System Verilog, clock voltage domain crossing design for testing DFT, ASIC Design, design rules, low power designs

C, Fpga, C++, Embedded Linux, Git, Python, Electrical codes, Safety Standards, Power Electronics, Communication Protocols, Digital control systems, VHDL, Tool chains, PPE’s Safety ESD Hazards, Signal Processing

code coverage , Oops, Usb, Networking, Cpu, DDR, Pcie, Verilog, Ethernet, Arm, LINT, cdc, SV, SV METH, C tests, Axi, AMBA, spyglass, VHDL, SoC Verification, Graphics, RTL Coding, AHB