Senior ASIC RTL Engineer

The Senior ASIC Engineer will be responsible for RTL design, subsystem/IP integration, and ensuring high-quality SoC implementations. The role involves working with multiple IP blocks, performing static checks, supporting synthesis, and collaborating with verification, DFT, and software teams to resolve design queries.

Key Responsibilities

• Design and implement SoC subsystems and IP using Verilog/SystemVerilog.
• Perform subsystem/cluster and SoC-level IP integration.
• Conduct RTL quality checks including linting and clock domain crossing (CDC) analysis.
• Support synthesis, timing analysis, and low-power optimizations.
• Apply knowledge of AMBA bus protocols (AXI, AHB, ATB, APB) in design and integration.
• Work with interface protocols including PCIe, DDR, Ethernet, I2C, UART, and SPI.
• Set up and utilize tools like Spyglass (Lint/CDC), Synopsys Design Compiler (DC), Verdi/Xcellium.
• Write and maintain scripts using Makeflow, Perl, Shell, or Python for automation and flow management.
• Support physical design, verification, DFT, and software teams on design-related queries.
• Create and review design documents for multiple subsystems to ensure design correctness and adherence to standards.
• Debug issues across multiple subsystems and provide guidance for design improvements.

Must-Have Experience

• Expertise in SoC subsystem and IP design.
• Strong RTL design skills using Verilog/SystemVerilog.
• In-depth knowledge of RTL quality checks (Lint, CDC).
• Familiarity with AMBA bus protocols and basic timing concepts.
• Hands-on experience with one or more interface protocols: PCIe, DDR, Ethernet, I2C, UART, SPI.
• Experience with industry-standard tools like Spyglass, Synopsys DC, Verdi/Xcellium.
• Scripting knowledge (Makeflow, Perl, Shell, Python).