Synopsys IC Validator, 7nm FinFET technology, multi-patterning awareness, Cadence Virtuoso Layout Suite, Cadence Pegasus, high-speed analog and mixed-signal layout design, Calibre DRC LVS PEX, device matching, LVS, extracted netlists, Custom Compiler, ERC checks, DRC, parasitic optimization, reliability rules

reliability driven layout practices, Calibre, analog mixed-signal IC layout, PEX, DRC, parasitic-aware layout, antenna rules, post-layout simulation correlation, LVS, Cadence Virtuoso

FinFET GAA layout concepts, Cadence Virtuoso Custom Layout, Calibre PVS, advanced-node analog custom layout, PEX, parasitic optimization, physical verification flows, post-layout simulation correlation, matching shielding guard rings isolation

Design Rule Checks (DRC), Layout-versus-Schematic (LVS), Analog Circuit Design, Post-silicon debug, Custom Layout, Floor Planning, Foundry-specific design guidelines, Analog Layout Design, Device matching, Parasitic-aware layout optimization

caliber , Verification Tools, Layout Design, Cadence Virtuoso

Perl, Python, Tcl, Skill, Calibre PVS, Cadence Virtuoso, High-voltage process technologies, IR drop, Physical verification tools, PEX, Reliability-aware layout, Antenna density, High-current routing, Layout methodology improvements, LVS, Parasitic control, Latch-up prevention, Electromigration, Noise isolation, Thermal effects, ERC, DRC, Extraction and reliability tools, Tape-out readiness, Guard rings