RTL Design Verification Engineer

RTL Design Verification Engineer

Experience- 3+ years

Location-Bangalore

Key Responsibilities

Functional Verification

Develop and execute RTL verification plans based on design specifications and system requirements.

Build, enhance, and maintain System Verilog / UVM‑based testbenches (drivers, monitors, scoreboards, checkers).

Write directed and constrained‑random test cases for functional, corner‑case, and negative testing.

Debug RTL and testbench issues using waveform analysis and simulation tools.

Coverage & Quality Closure

Drive code coverage (line, branch, FSM, toggle) and functional coverage to closure targets.

Analyze coverage gaps and implement additional test scenarios for closure.

Participate in RTL release readiness activities, ensuring verification sign‑off before major RTL drops.

Collaboration & Execution

Work closely with RTL Design Engineers to review design intent, clarify corner cases, and resolve bugs.

Coordinate with DFT and System teams for test‑mode, reset, and power‑sequence verification.

Support incremental RTL releases and regressions during active development phases.

Required Technical Skills

Languages & Methodologies

Strong proficiency in System Verilog and UVM

Good understanding of Verilog RTL

Experience with directed and constrained‑random verification

Tools

RTL simulators (e.g., VCS, Xcelium, Questa)

Debug tools and waveform viewers

Code and functional coverage tools

Regression and CI‑based verification flows (basic familiarity)

Scripting

Basic working knowledge of Python / Perl / Tcl for testbench or flow automation

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