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RTL Design Lead
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Below is the JD for RTL engineers. We need to build strong RTL team.
Job ID: 153641787
Skills:
Ovm, System Verilog, Synthesis Design Compiler, RTL Verilog, Static Timing Analysis PrimeTime, Power analysis tools, Uvm
Skills:
Scripting Language, python, Program Analysis, Verilog, Computer Architecture, benchmark characterization, Benchmarking, workloads characterization, microarchitectural timing simulator, x86 assembly language programming, VHDL, Bottleneck Analysis, hardware performance counters
Skills:
Pcie, timing-aware micro-architecture, UCIe, high-speed lane alignment, SystemVerilog RTL, CXL, physical-closure collaboration, deskew, design-for-test
Skills:
test equipment , Usb, Spi, Gpio, Pcie, Perl, Verilog, Debugging, Ethernet, I2c, Python, Tcl, HW testing, traffic analysers, DDR SDRAM, Memory architectures, Rtl Design, VHDL, Xilinx technology and tools, test generators, DMA technologies
Skills:
Verilog, multi-clock designs, Synthesis, formal verification, ECO fixes, SoC clocking reset architecture, Logic design RTL coding, SoC design and integration, Timing Concepts, asynchronous interfaces, System-Verilog
