Ovm, System Verilog, Synthesis Design Compiler, RTL Verilog, Static Timing Analysis PrimeTime, Power analysis tools, Uvm

Scripting Language, python, Program Analysis, Verilog, Computer Architecture, benchmark characterization, Benchmarking, workloads characterization, microarchitectural timing simulator, x86 assembly language programming, VHDL, Bottleneck Analysis, hardware performance counters

Pcie, timing-aware micro-architecture, UCIe, high-speed lane alignment, SystemVerilog RTL, CXL, physical-closure collaboration, deskew, design-for-test

test equipment , Usb, Spi, Gpio, Pcie, Perl, Verilog, Debugging, Ethernet, I2c, Python, Tcl, HW testing, traffic analysers, DDR SDRAM, Memory architectures, Rtl Design, VHDL, Xilinx technology and tools, test generators, DMA technologies

Verilog, multi-clock designs, Synthesis, formal verification, ECO fixes, SoC clocking reset architecture, Logic design RTL coding, SoC design and integration, Timing Concepts, asynchronous interfaces, System-Verilog

Logic Design, Verilog, Microprocessors, low power design, LINT, cdc, Design Compiler, Memory controller designs, AMBA protocols, ASIC RTL Design, primetime, Asynchronous interface, Synthesis, Axi, timing concepts for ASIC, APB, RTL Coding, micro-architecture, Multi Clock designs, AHB, System-Verilog

Verilog, SOC design, Gds, NC sim, RTL, NC Verilog

Verilog, Ethernet, Python, Tcl, FPGA design flow using Vivado, VHDL, SpaceWire, FPGA SoC development kits, Electronic test equipment, Libero EDA tools, Camera link