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Below is the JD for RTL engineers. We need to build strong RTL team.
Job ID: 148869763
Skills:
Perl, Verilog, System Verilog, Python, Tcl, quartus, VHDL, Vivado, Altera FPGA design tools
Skills:
C, Vcs, Perl, Verilog, cdc, Hardware Emulation Platforms, ASIC SoC development, systemverilog, Rtl Design, spyglass, EVE, Veloce, formal verification
Skills:
C, Vcs, Perl, Verilog, Hardware Emulation Platforms, cdc, ASIC SoC development cycle, systemverilog, Rtl Design, spyglass, EVE, ASIC Design, Veloce, formal verification
Skills:
rtl development , Verilog, System Verilog, spyglass, VHDL, CDC Spyglass, System Verilog Assertion, Linting
Skills:
Perl, Verilog, Python, Tcl, microarchitecture development, Synthesis, cdc, systemverilog, Rtl Design, RDC, EDA Tools, LINT, low-power methodologies, STA concepts
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