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RTL Design Lead

This job is no longer accepting applications

  • Posted 3 days ago

Job Description

Below is the JD for RTL engineers. We need to build strong RTL team.

  • Minimum 8+ years of work experience in ASIC RTL Design, Synthesis, STA & FV
  • Experience in Logic design/micro-architecture/RTL coding is a must.
  • Must have hands on experience with design and integration of complex multi clock domain blocks
  • Experience in Verilog/System-Verilog is a must.
  • Should have knowledge of AMBA protocols - AXI, AHB, APB, clocking/reset/debug architecture
  • Hands on experience in Multi Clock designs, Asynchronous interface is a must.
  • Experience in using the tools in ASIC development such as Lint, CDC, Design compiler and Primetime is required.
  • Work closely with the Design verification and validation teams for pre/post Silicon debug
  • Hands on experience in Low power design is preferable
  • Experience in Synthesis / Understanding of timing concepts for ASIC is must

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Job ID: 148869763

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