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RTL Design Lead Hardware Engineer

Altera
Bengaluru, India

Skills:

Perl, Verilog, System Verilog, Python, Tcl, quartus, VHDL, Vivado, Altera FPGA design tools

Early Applicant

ASIC Engineering Technical Leader | RTL Design Lead

Cisco Live
Bengaluru, India

Skills:

C, Vcs, Perl, Verilog, cdc, Hardware Emulation Platforms, ASIC SoC development, systemverilog, Rtl Design, spyglass, EVE, Veloce, formal verification

Early Applicant

ASIC Engineering Technical Leader | RTL Design Lead

Cisco Home
Bengaluru, India

Skills:

C, Vcs, Perl, Verilog, Hardware Emulation Platforms, cdc, ASIC SoC development cycle, systemverilog, Rtl Design, spyglass, EVE, ASIC Design, Veloce, formal verification

Early Applicant

RTL Design Engineer, Sr Lead

Qualcomm
Q
Bengaluru, India

Skills:

rtl development , Verilog, System Verilog, spyglass, VHDL, CDC Spyglass, System Verilog Assertion, Linting

Early Applicant

Lead ASIC RTL Design Engineer

leadsoc technologies pvt ltd
Bengaluru, India

Skills:

Perl, Verilog, Python, Tcl, microarchitecture development, Synthesis, cdc, systemverilog, Rtl Design, RDC, EDA Tools, LINT, low-power methodologies, STA concepts

Early Applicant

Lead-FPGA/RTL Design

Digantara
Bengaluru, India

Skills:

Verilog, Ethernet, Python, Tcl, FPGA design flow using Vivado, VHDL, FPGA SoC development kits, SpaceWire, Electronic test equipment, Libero EDA tools, Camera link

Early Applicant

MTS SILICON DESIGN ENGINEER ( SOC Low Power-RTL lead)

AMD
Bengaluru

Skills:

Debugging, Rtl Design, SoC ASIC

Early Applicant
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