RTL Design Engineer

evnek

10-12 Years

Bengaluru, India

Early Applicant

Posted 3 months ago
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Job Description

Job Role: RTL Design Engineer

Experience: 10+yrs

Location: Bengaluru

Notice Period: 30days max

Role Summary
We are seeking an experienced RTL Design Engineer to join our team and contribute to the RTL design and development of the signal processing path for Aeva's advanced 4-D Lidar processing chip. In this role, you will design, implement, and integrate key sub-components into both ASIC and FPGA platforms, ensuring performance, efficiency, and robustness.

Key Responsibilities

Design and develop custom components for the digital signal processing pipeline, including filters, FFTs, control logic, and related modules.
Create micro-architecture specifications, write SystemVerilog RTL code, and perform testing and validation for Aeva-specific components.
Integrate advanced features for functional safety, reliability, and robustness.
Deliver high-performance, low-power, and scalable designs that meet stringent quality standards.
Collaborate with architects, design engineers, verification engineers, and system software teams to ensure SoC functional, performance, and power objectives are achieved.

Qualifications

10+ years of experience designing DSP architectures, algorithms, and signal processing functionalities in ASICs and/or FPGAs.
Proven ability to meet high-performance and low-power design targets.
Proficiency in SystemVerilog RTL coding.
Hands-on experience with AMBA protocols.
Strong problem-solving skills and a passion for implementing innovative processes and methodologies.

Preferred Skills

Experience with Matlab, NumPy, C, and/or C++.
Knowledge of LPDDR, Ethernet, MIPI, and high-speed SerDes.
FPGA design experience and pre-silicon validation using emulation platforms (e.g., Cadence Palladium, Mentor Veloce, Synopsys Zebu).
Post-silicon bring-up and validation expertise.
Experience in diagnostics firmware development and validation.

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About Company

evnek

Job ID: 128392345

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Last Updated: 21-07-2026 00:12:32 AM

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