RTL Design Engineer
- Posted 2 months ago
- Be among the first 10 applicants
Job Description
Job Role: RTL Design Engineer
Experience: 10+yrs
Location: Bengaluru
Notice Period: 30days max
We are seeking an experienced RTL Design Engineer to join our team and contribute to the RTL design and development of the signal processing path for Aeva's advanced 4-D Lidar processing chip. In this role, you will design, implement, and integrate key sub-components into both ASIC and FPGA platforms, ensuring performance, efficiency, and robustness.
Key Responsibilities
- Design and develop custom components for the digital signal processing pipeline, including filters, FFTs, control logic, and related modules.
- Create micro-architecture specifications, write SystemVerilog RTL code, and perform testing and validation for Aeva-specific components.
- Integrate advanced features for functional safety, reliability, and robustness.
- Deliver high-performance, low-power, and scalable designs that meet stringent quality standards.
- Collaborate with architects, design engineers, verification engineers, and system software teams to ensure SoC functional, performance, and power objectives are achieved.
Qualifications
- 10+ years of experience designing DSP architectures, algorithms, and signal processing functionalities in ASICs and/or FPGAs.
- Proven ability to meet high-performance and low-power design targets.
- Proficiency in SystemVerilog RTL coding.
- Hands-on experience with AMBA protocols.
- Strong problem-solving skills and a passion for implementing innovative processes and methodologies.
Preferred Skills
- Experience with Matlab, NumPy, C, and/or C++.
- Knowledge of LPDDR, Ethernet, MIPI, and high-speed SerDes.
- FPGA design experience and pre-silicon validation using emulation platforms (e.g., Cadence Palladium, Mentor Veloce, Synopsys Zebu).
- Post-silicon bring-up and validation expertise.
- Experience in diagnostics firmware development and validation.
More Info
Key Skills
LPDDR
high-speed SerDes
Cadence Palladium
Synopsys Zebu
MIPI
SystemVerilog RTL
Mentor Veloce
pre-silicon validation
AMBA protocols
About Company
Skills:
Verilog, Rtl Design, RTL Coding, Micro-architecture, systemverilog, RTL Design Engineer
Early Applicant
Skills:
Perl, Shell scripting, Python, Sta, SDC constraints, RTL design using Verilog, ASIC SoC development, Timing Analysis, systemverilog, digital design concepts, VHDL, Functional Verification, RTL debugging, UVM-based verification environments, Timing Closure, synthesis flows
Skills:
C, Clearcase, Cryptography, Aes, Encryption, Clearquest, Perl, Verilog, Python, System Verilog, LINT, cdc, RTL design using Verilog, hash functions, GMAC, signatures, LEC, SHA, private key, ASIC development tools, random number generator
Skills:
Debugging, Verilog, Computer Architecture, LINT, cdc, RTL simulation, Execution units, Synthesis-aware coding, Caches, RISC-V ISA, CPU microarchitecture, systemverilog, Rtl Design, Memory hierarchy, CPU pipelines, CPU performance optimization, RTL quality checks, Instruction decoding, Microarchitectural trade-offs, ARM processor architecture, formal verification
Skills:
Matlab Simulink, RTL Verilog, mixed-signal verification, digital PWM modulators, digital design tools, systemverilog