Rtl Design, high-speed interfaces, thermal monitoring integration, power management, clock-gating, micro-architecture, systemverilog, embedded microcontroller integration, reset-domain architecture

Usb, Verilog, Ethernet, Pcie, DDR, VHDL, UCIe, LINT, systemverilog, cdc, Sta, Synthesis, formal checking, HBM, RDC, spyglass

Ecos, Tcl, Verilog, Python, DFT hooks, UPF, systemverilog, Ace, micro-architecture, low-power techniques, SVA, AHB, synthesis constraints, Timing Closure, APB, Axi, AMBA standard bus protocols

Verilog, Microprocessors, Usb, Logic Design, Pcie, LINT, cdc, pad ring, SoC clocking, Design Compiler, Asynchronous interface, Synthesis, SDCC, RTL Coding, micro-architecture, Low power SoC design, System-Verilog, constraint development, SOC design, chip level floorplan, Memory controller designs, reset debug architecture, AMBA protocols, primetime, Axi, APB, timing concepts for ASIC, Timing Closure, Multi Clock designs, AHB

Verilog, System Verilog, Jtag, C, Uvm, SOC RTL Design Verification

Uart, Spi, Verilog, I2c, LINT, cdc, MAS development, Sub-system design, SoC integration, ip design, Quality check flows, AMBA bus protocols, Axi, APB, RTL Coding, Medium complexity protocol, AHB, Microarchitecture