Verilog, Rtl Design, RTL Coding, Micro-architecture, systemverilog, RTL Design Engineer

Perl, Shell scripting, Python, Sta, SDC constraints, RTL design using Verilog, ASIC SoC development, Timing Analysis, systemverilog, digital design concepts, VHDL, Functional Verification, RTL debugging, UVM-based verification environments, Timing Closure, synthesis flows

C, Clearcase, Cryptography, Aes, Encryption, Clearquest, Perl, Verilog, Python, System Verilog, LINT, cdc, RTL design using Verilog, hash functions, GMAC, signatures, LEC, SHA, private key, ASIC development tools, random number generator

Debugging, Verilog, Computer Architecture, LINT, cdc, RTL simulation, Execution units, Synthesis-aware coding, Caches, RISC-V ISA, CPU microarchitecture, systemverilog, Rtl Design, Memory hierarchy, CPU pipelines, CPU performance optimization, RTL quality checks, Instruction decoding, Microarchitectural trade-offs, ARM processor architecture, formal verification

Matlab Simulink, RTL Verilog, mixed-signal verification, digital PWM modulators, digital design tools, systemverilog

Unix, Usb, Linux, Tcl, Ruby, Sata, Ethernet, Perl, Pcie, DDR, front-end EDA tools, high speed IO controller design, ASIC Design, Verilog Hdl

DDR, Pcie, Verilog, synthesis constraints, coherency memory subsystems, clock reset expertise, AMBA protocols, systemverilog, ECO flows, performance power analysis, Dft, ASIC RTL, cross-team collaboration, security blocks, low-power design, micro-architecture, SVA

Jtag, C, Verilog, System Verilog, Uvm, SOC RTL Design Verification