RTL Design Engineer

Role

Job Responsibility

1. IP Block Ownership: Lead the end-to-end integration of a designated block. Design meeting functional, performance, power and area targets.

2. SOC Flow Execution: Very good in flow stack - Spyglass-Lint, CDC , DC synthesis and VCLP.

3. Power-Management Expertise (Preferred): Good knowledge and experience about UPF

4. Cross-Team Support: Provide design-constraint assistance and technical guidance to DV, PD and DFT team

5. Good debugging skills

6. Clear technical communication and documentation

REQUIRED SKILLS

Minimum of 7 years of experience,

VLSI SoC/IP Frontend design,

SoC Full Chip Integration For RTL lead position

IP Block Integration,

Spyglass-Lint, CDC Analysis, Synopsys Design Compiler (DC) synthesis, VCLP (Verification-Constraint-Lint-Power) tools

Strong coding skills - Verilog / System Verilog / VHDL

Nice to Have

Analytical Mindset

Team player , comfortable working in a fast-paced, deadline-driven environment