RTL Design Engineer
- Posted a month ago
- Be among the first 40 applicants
Job Description
Job Title: RTL Design Engineers
Exp Level: 2-3 yrs
Loctaion: Hyderabad
Job Description:
- Seeking a motivated RTL Design Engineer to develop, integrate, and verify digital logic using Verilog/SystemVerilog.
- Responsibilities include ASIC/SoC IP integration, linting, synthesis, and working closely with verification teams.
- Requires strong fundamentals in digital design, timing closure, and understanding of the ASIC flow.
- You'll debug simulation failures, implement ECOs, and support gate-level simulations.
- Collaborate with cross-functional teams (SW, DV, Physical Design) to achieve tapeout goals.
- Bachelor's or Master's degree in engineering in EE/CS is essential, along with 2-3 years of relevant experience.
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Key Skills
gate-level simulations
linting
IP integration
About Company
Skills:
Verilog, Rtl Design, RTL Coding, Micro-architecture, systemverilog, RTL Design Engineer
Early Applicant
Skills:
Rtl Design, RTL quality checks, Micro-architecture design, SOC integration
Skills:
Verilog, Fpga, VHDL, systemverilog, ASIC Design, Synthesis Tools, Timing Analysis, Verification Methodologies, Physical Design, low power design
Skills:
Verilog, Rtl Design, Logic analyzers, systemverilog, DDR memory controller calibration, Calibration algorithms
Skills:
Digital Logic Design, Rtl Design, SOC Integration, RTL quality checks, Constraints for Subsystem IP, ip design, Processor peripherals