RTL Design Engineer
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Job Title: RTL Design Engineers
Exp Level: 2-3 yrs
Loctaion: Hyderabad
Job Description:
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Job ID: 144751197
Skills:
Perl, Verilog, Python, Makefiles, RTL Build flows, Chip Design Functions, SoC Verification, Physical Design, Rtl Design, Dft, Synthesis, System-On-Chip design implementation flow
Skills:
Rtl Design, UFS, Octal SPI, RTL quality checks, SOC integration, SDIO
Skills:
Verilog, Ethernet Protocols, LINT, Rtl Design, spyglass, Synthesis, cdc, RDC, PPA optimization, systemverilog
Skills:
Automation Frameworks, Sta, LINT, Memory operation, Synchronous design concepts, power analysis, SoC design flows, CMOS Circuit Design, Rtl Design, spyglass, Synthesis, device physics, CDC methodologies
Skills:
Python Scripting, Git, PrimeTime or equivalent tools, Modern SOC tools including Spyglass, Version control systems such as Perforce, ASIC design flow, Low power digital design and analysis, Digital Design, C embedded experience, VCS simulation, Cadence Conformal, ICManage, ASIC design in sub-20nm technology nodes, Questa CDC, RTL design in Verilog, Circuit timing STA
